`timescale 1ns / 1ps

module DELAY_BITS
    #(
        parameter n_delay = 1,
        parameter SIZE = 8
    )(
        input clk,
        input rst,
        input bit_in,
        output bit_out
    );

    localparam ZERO = 512'b0;
    parameter BIT_LEN = n_delay + 1;
    // localparam SIZE = 8;
    reg[SIZE-1:0] bit_buf;

    // always@( posedge clk or posedge rst ) begin
    always@( negedge clk or posedge rst ) begin
        if( rst ) begin
            bit_buf[SIZE-1:0] <= ZERO[SIZE-1:0];
        end
        else begin
            bit_buf[SIZE-1:0] <= {bit_buf[SIZE-2:0], bit_in};
        end
    end

    assign bit_out = bit_buf[n_delay];

    // reg bit_out_r;
    // always@(bit_buf[n_delay]) begin
    //     bit_out_r <= bit_buf[n_delay];
    // end

    // assign bit_out = bit_out_r;
    // assign bit_out = 1'b1;

endmodule
